A VLSI Implementation of Real-time 8×8 2-D DCT Processor for the Subprimary Rate Video Codec
Vol. 15, No. 1, pp. 58-70, Jan. 1990
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Cite this article
[IEEE Style]
권용무 and 김형곤, "A VLSI Implementation of Real-time 8×8 2-D DCT Processor for the Subprimary Rate Video Codec," The Journal of Korean Institute of Communications and Information Sciences, vol. 15, no. 1, pp. 58-70, 1990. DOI: .
[ACM Style]
권용무 and 김형곤. 1990. A VLSI Implementation of Real-time 8×8 2-D DCT Processor for the Subprimary Rate Video Codec. The Journal of Korean Institute of Communications and Information Sciences, 15, 1, (1990), 58-70. DOI: .
[KICS Style]
권용무 and 김형곤, "A VLSI Implementation of Real-time 8×8 2-D DCT Processor for the Subprimary Rate Video Codec," The Journal of Korean Institute of Communications and Information Sciences, vol. 15, no. 1, pp. 58-70, 1. 1990.
pISSN : 1226 - 4717
eISSN : 2287 - 3880