A Study on the Test Circuit Design and Development of Algorithm for Parallel RAM Testing
Vol. 17, No. 7, pp. 666-676, Jul. 1992
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Cite this article
[IEEE Style]
조현묵, 백경갑, 백인천, 차균현, "A Study on the Test Circuit Design and Development of Algorithm for Parallel RAM Testing," The Journal of Korean Institute of Communications and Information Sciences, vol. 17, no. 7, pp. 666-676, 1992. DOI: .
[ACM Style]
조현묵, 백경갑, 백인천, and 차균현. 1992. A Study on the Test Circuit Design and Development of Algorithm for Parallel RAM Testing. The Journal of Korean Institute of Communications and Information Sciences, 17, 7, (1992), 666-676. DOI: .
[KICS Style]
조현묵, 백경갑, 백인천, 차균현, "A Study on the Test Circuit Design and Development of Algorithm for Parallel RAM Testing," The Journal of Korean Institute of Communications and Information Sciences, vol. 17, no. 7, pp. 666-676, 7. 1992.
pISSN : 1226 - 4717
eISSN : 2287 - 3880