An Efficient VLSI Architecture for High Speed Matrix Transposition
Vol. 21, No. 12, pp. 3256-3264, Dec. 1996
Statistics
Cumulative Counts from November, 2022
Multiple requests among the same browser session are counted as one view. If you mouse over a chart, the values of data points will be shown.
Multiple requests among the same browser session are counted as one view. If you mouse over a chart, the values of data points will be shown.
|
|
Cite this article
[IEEE Style]
김견수, 장순화, 김재호, 손경식, "An Efficient VLSI Architecture for High Speed Matrix Transposition," The Journal of Korean Institute of Communications and Information Sciences, vol. 21, no. 12, pp. 3256-3264, 1996. DOI: .
[ACM Style]
김견수, 장순화, 김재호, and 손경식. 1996. An Efficient VLSI Architecture for High Speed Matrix Transposition. The Journal of Korean Institute of Communications and Information Sciences, 21, 12, (1996), 3256-3264. DOI: .
[KICS Style]
김견수, 장순화, 김재호, 손경식, "An Efficient VLSI Architecture for High Speed Matrix Transposition," The Journal of Korean Institute of Communications and Information Sciences, vol. 21, no. 12, pp. 3256-3264, 12. 1996.
pISSN : 1226 - 4717
eISSN : 2287 - 3880