A 16 x 16 bit Parallel Multiplier Architecture using High Speed 4 : 2 Compressor
Vol. 25, No. 6, pp. 18-24, Jun. 2000
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Cite this article
[IEEE Style]
진용선 and 정정화, "A 16 x 16 bit Parallel Multiplier Architecture using High Speed 4 : 2 Compressor," The Journal of Korean Institute of Communications and Information Sciences, vol. 25, no. 6, pp. 18-24, 2000. DOI: .
[ACM Style]
진용선 and 정정화. 2000. A 16 x 16 bit Parallel Multiplier Architecture using High Speed 4 : 2 Compressor. The Journal of Korean Institute of Communications and Information Sciences, 25, 6, (2000), 18-24. DOI: .
[KICS Style]
진용선 and 정정화, "A 16 x 16 bit Parallel Multiplier Architecture using High Speed 4 : 2 Compressor," The Journal of Korean Institute of Communications and Information Sciences, vol. 25, no. 6, pp. 18-24, 6. 2000.
pISSN : 1226 - 4717
eISSN : 2287 - 3880