English Digital Signal Processing Circuit in HD Monitor using Synchronization Signal Optimization 


Vol. 28,  No. 11, pp. 1152-1160, Nov.  2003


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  Abstract

Start The current paper proposes an improved HD(High Definition) monitor that can support a signal input with various resolutions. Due to the inadequate performance of the built-in digital PLL(Phase-Locked Loop) of an ADC(Analog to Digital Converter) and poor tolerance of ADC ICs, there are problems in the stable processing of synchronization signals with various input signals. Accordingly, the proposed synchronization signal optimization technique regenerates the horizontal synchronization signal in the vertical blanking interval based on the regularity of the synchronization signal, ie. the timing of the falling edge signal remains constant, thereby solving the above problem and minimizing the interference of the system. As a result, the proposed system can stabilize various synchronization signals with different resolution modes.

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  Cite this article

[IEEE Style]

S. Cheon, I. Kim, H. Lee, Y. Ha, "English Digital Signal Processing Circuit in HD Monitor using Synchronization Signal Optimization," The Journal of Korean Institute of Communications and Information Sciences, vol. 28, no. 11, pp. 1152-1160, 2003. DOI: .

[ACM Style]

Sung-Ryoul Cheon, Ik-Hwan Kim, Ho-Keun Lee, and Yeong-Ho Ha. 2003. English Digital Signal Processing Circuit in HD Monitor using Synchronization Signal Optimization. The Journal of Korean Institute of Communications and Information Sciences, 28, 11, (2003), 1152-1160. DOI: .

[KICS Style]

Sung-Ryoul Cheon, Ik-Hwan Kim, Ho-Keun Lee, Yeong-Ho Ha, "English Digital Signal Processing Circuit in HD Monitor using Synchronization Signal Optimization," The Journal of Korean Institute of Communications and Information Sciences, vol. 28, no. 11, pp. 1152-1160, 11. 2003.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880