A Study on the Exclusive-OR-based Technology Mapping Method in FPGA 


Vol. 28,  No. 11, pp. 936-944, Nov.  2003


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  Abstract

In this paper, we propose an AND/XOR-based technology mapping method for field programmable gate arrays (FPGAs). Due to the fixed size of the programmable blocks in an FPGA, decomposing a circuit into sub-circuits with appropriate number of inputs can achieve excellent implementation efficiency. Specifically, the proposed technology mapping method is based on Davio expansion theorem to decompose a given Boolean circuit. The AND/XOR nature of the proposed method allows it to operate on XOR intensive circuits. such as error detecting/correcting, data encryption/decryption, and arithmetic circuits. efficiently.
We conduct experiments using MCNC benchmark circuits. When using the proposed approach, the number of CLBs (configurable logic blocks) is reduced by 67.6 % (compared to speed-optimized results) and 57.7 %(compared to area-optimized results), total equivalent gate counts are reduced by 65.5 %. maximum combinational path delay is reduced by 56.7 %. and maximum net delay is reduced by 80.5 % compared to conventional methods.

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  Cite this article

[IEEE Style]

S. Ko, "A Study on the Exclusive-OR-based Technology Mapping Method in FPGA," The Journal of Korean Institute of Communications and Information Sciences, vol. 28, no. 11, pp. 936-944, 2003. DOI: .

[ACM Style]

Seok-Bum Ko. 2003. A Study on the Exclusive-OR-based Technology Mapping Method in FPGA. The Journal of Korean Institute of Communications and Information Sciences, 28, 11, (2003), 936-944. DOI: .

[KICS Style]

Seok-Bum Ko, "A Study on the Exclusive-OR-based Technology Mapping Method in FPGA," The Journal of Korean Institute of Communications and Information Sciences, vol. 28, no. 11, pp. 936-944, 11. 2003.