Design and Implementation of 8b/1Ob Encoder/Decoder for Serial ATA 


Vol. 29,  No. 1, pp. 93-98, Jan.  2004


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  Abstract

Serial ATA interface is inexpensive comparatively and performance is superior. So it is suitable technology in demand that now require data transmission and throughput of high speed. This paper describes a design and implementation of Serial ATA Link layer about error detection and 8b/1Ob encoder/decoder for DC balance in frequency 150MHz. The 8b/1Ob Encoder is partitioned into a 5b/6b plus a 3b/4b coder. The logical model of the block is described by using Verilog HDL at register transistor level and the verified HDL is synthesized using standard cell libraries. And it is fabricated with O.35㎛ Standard CMOS Cell library and the chip size is about 1500㎛ * 15OO㎛. The function of this chip has been verified and tested using testboard with FPGA equipment and IDEC ATS2 test equipment. It is used to frequency of 100MHz in verification processes and supply voltage 3.3V. The result of testing is well on the system clock 1OOMHz. The designed and verified each blocks may be used IP in the field of high speed serial data communication.

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  Cite this article

[IEEE Style]

J. Heo, N. Park, S. Park, "Design and Implementation of 8b/1Ob Encoder/Decoder for Serial ATA," The Journal of Korean Institute of Communications and Information Sciences, vol. 29, no. 1, pp. 93-98, 2004. DOI: .

[ACM Style]

Jung-Hwa Heo, Nho-Kyung Park, and Sang-Bong Park. 2004. Design and Implementation of 8b/1Ob Encoder/Decoder for Serial ATA. The Journal of Korean Institute of Communications and Information Sciences, 29, 1, (2004), 93-98. DOI: .

[KICS Style]

Jung-Hwa Heo, Nho-Kyung Park, Sang-Bong Park, "Design and Implementation of 8b/1Ob Encoder/Decoder for Serial ATA," The Journal of Korean Institute of Communications and Information Sciences, vol. 29, no. 1, pp. 93-98, 1. 2004.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880