A Matched Filter with Two Data Flow Paths for Searching Sychronization in DSSS 


Vol. 29,  No. 1, pp. 99-106, Jan.  2004


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  Abstract

In this paper, the matched filter for searching initial synchronization in DSSS (direct sequence spread spectrum) receiver is studied. The matched filter with a single data flow path is described which can be presented by HDL (Hardware Description Language). In order to improve the processing time of operations for the filter, equations are arranged to represent two data flow paths and the associated hardware model is proposed. The model has an architecture based on parallelism and pipeline for fast processing, in which two data flow paths with a series of memory, multiplier and accumulator are placed in parallel. The performance of the model is analyzed and compared with the matched filter with a single data flow path.

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  Cite this article

[IEEE Style]

M. Song, "A Matched Filter with Two Data Flow Paths for Searching Sychronization in DSSS," The Journal of Korean Institute of Communications and Information Sciences, vol. 29, no. 1, pp. 99-106, 2004. DOI: .

[ACM Style]

Myong-Lyol Song. 2004. A Matched Filter with Two Data Flow Paths for Searching Sychronization in DSSS. The Journal of Korean Institute of Communications and Information Sciences, 29, 1, (2004), 99-106. DOI: .

[KICS Style]

Myong-Lyol Song, "A Matched Filter with Two Data Flow Paths for Searching Sychronization in DSSS," The Journal of Korean Institute of Communications and Information Sciences, vol. 29, no. 1, pp. 99-106, 1. 2004.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880