Low-power/high-speed DCT structure using common sub-expression sharing 


Vol. 29,  No. 1, pp. 119-128, Jan.  2004


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  Abstract

In this paper, a low-power 8-point DCT structure is proposed using add and shift operations. Proposed structure adopts 4 cycles for complete 8-point DCT in order to minimize size of hardware and to enable high-speed processing. In the structure, hardware for the first cycle can be shared in the next 3 cycles since all columns in the DCT coefficient matrix are common except sign. Conventional DCT structures implemented with only add and shift operation use CSD(Canonic Signed Digit) form coefficients to reduce the number of adders. To reduce the number of adders further, we propose a new structure using common sub-expression sharing techniques. With this techniques, the proposed 8-point DCT structure achieves 19.5% adder reduction comparison to the conventional structure using only CSD coefficient form.

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  Cite this article

[IEEE Style]

Y. Jang and S. Yang, "Low-power/high-speed DCT structure using common sub-expression sharing," The Journal of Korean Institute of Communications and Information Sciences, vol. 29, no. 1, pp. 119-128, 2004. DOI: .

[ACM Style]

Young-Beom Jang and Se-Jung Yang. 2004. Low-power/high-speed DCT structure using common sub-expression sharing. The Journal of Korean Institute of Communications and Information Sciences, 29, 1, (2004), 119-128. DOI: .

[KICS Style]

Young-Beom Jang and Se-Jung Yang, "Low-power/high-speed DCT structure using common sub-expression sharing," The Journal of Korean Institute of Communications and Information Sciences, vol. 29, no. 1, pp. 119-128, 1. 2004.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880