The Design of GF(2m) Parallel Multiplier using data select methodology 


Vol. 28,  No. 2, pp. 102-109, Feb.  2003


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  Abstract

In this paper, the new multiplicative algorithm using standard basis over GF(2m) is proposed. The multiplicative process is simplified by data select method in proposed algorithm. After multiplicative operation, the terms of degree greater than m can be expressed as a polynomial of standard basis with degree less than m by irreducible polynomial. For circuit implementation of proposed algorithm, we design the circuit using multiplexer and show the example over GF(24). The proposed architectures are regular and simple extension for m. Also, the comparison result show that the proposed architecture is more simple than privious multipliers. Therefore, it well suited for VLSI realization and application other operation circuits.

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  Cite this article

[IEEE Style]

G. Byun, Y. Choi, H. Kim, "The Design of GF(2m) Parallel Multiplier using data select methodology," The Journal of Korean Institute of Communications and Information Sciences, vol. 28, no. 2, pp. 102-109, 2003. DOI: .

[ACM Style]

Gi-Young Byun, Young-Hee Choi, and Heong-Soo Kim. 2003. The Design of GF(2m) Parallel Multiplier using data select methodology. The Journal of Korean Institute of Communications and Information Sciences, 28, 2, (2003), 102-109. DOI: .

[KICS Style]

Gi-Young Byun, Young-Hee Choi, Heong-Soo Kim, "The Design of GF(2m) Parallel Multiplier using data select methodology," The Journal of Korean Institute of Communications and Information Sciences, vol. 28, no. 2, pp. 102-109, 2. 2003.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880