A Study on the hardware implementation of the 3GPP standard Turbo Decoder 


Vol. 28,  No. 3, pp. 215-223, Mar.  2003


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  Abstract

Turbo codes are selected as FEC(Forward error correction) codes with convolution code in 3GPP(3rd generation partnership project) and 3GPP2 standard of IMT2000. Especially, 1/3 turbo code with K=4 is employed for 3GPP standard. In this paper, we proposed a hardware structure of a turbo decoder and developed the decoder for 3GPP standard turbo code. For its efficient operation, we design a SOVA decoder by employing a register exchange decoding block and new path metric normalization block as a SISO constituent decoder. In addition, we estimate its performance under MATLAB 6.0 and designed the turbo decoder including control block, input control buffer, SOVA constituent decoder with VHDL. Finally, we synthesized the developed turbo decoder under Synopsys FPGA Express and verified it with ALTERA EPF200SRC240-3 FPGA device.

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  Cite this article

[IEEE Style]

J. Kim and D. Chung, "A Study on the hardware implementation of the 3GPP standard Turbo Decoder," The Journal of Korean Institute of Communications and Information Sciences, vol. 28, no. 3, pp. 215-223, 2003. DOI: .

[ACM Style]

Ju-Min Kim and Duck-Jin Chung. 2003. A Study on the hardware implementation of the 3GPP standard Turbo Decoder. The Journal of Korean Institute of Communications and Information Sciences, 28, 3, (2003), 215-223. DOI: .

[KICS Style]

Ju-Min Kim and Duck-Jin Chung, "A Study on the hardware implementation of the 3GPP standard Turbo Decoder," The Journal of Korean Institute of Communications and Information Sciences, vol. 28, no. 3, pp. 215-223, 3. 2003.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880