A Parallel Multiple Hashing Architecture for IP Address Lookup 


Vol. 29,  No. 2, pp. 158-166, Feb.  2004


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  Abstract

Address lookup is one of the most essential functions of the Internet routers and a very important feature in evaluating router performance. Due to the facts that the Internet traffic keeps growing and the number of routing table entries is continuously growing, efficient address-lookup mechanism is indispensable. In recent years, various fast address-lookup schemes have been proposed, but most of those schemes are not practical in terms of the memory size required for routing table and the complexity required in table update. In this paper, we have proposed a parallel IP address lookup architecture based on multiple hashing. The proposed scheme has advantages in required memory size, the number of memory accesses, and table update. We have evaluated the performance of the proposed scheme through simulation using data from MAE-WEST router. The simulation result shows that the proposed scheme requires a single memory access for the address lookup of each route when 203kbytes of memory and a few-hundred-entry TCAM are used.

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  Cite this article

[IEEE Style]

Y. Jung, B. Lee, H. Lim, "A Parallel Multiple Hashing Architecture for IP Address Lookup," The Journal of Korean Institute of Communications and Information Sciences, vol. 29, no. 2, pp. 158-166, 2004. DOI: .

[ACM Style]

Yeo-Jin Jung, Bomi Lee, and Hyesook Lim. 2004. A Parallel Multiple Hashing Architecture for IP Address Lookup. The Journal of Korean Institute of Communications and Information Sciences, 29, 2, (2004), 158-166. DOI: .

[KICS Style]

Yeo-Jin Jung, Bomi Lee, Hyesook Lim, "A Parallel Multiple Hashing Architecture for IP Address Lookup," The Journal of Korean Institute of Communications and Information Sciences, vol. 29, no. 2, pp. 158-166, 2. 2004.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880