A 155 Mb/s BiCMOS Multiplexer-Demultiplexer IC 


Vol. 28,  No. 1, pp. 47-53, Jan.  2003


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  Abstract

This paper describes the design of a 155 Mb/s multiplexer-demultiplexer chip. This device for a 2.5 Gb/s SDH based transmission system is to interleave the parallel data of 51 Mb/s into 155 Mb/s serial data output, and is to deinterleave a serial input bit stream of 155 Mb/s into the parallel output of 51 Mb/s The input and output of the device are TTL compatible at the low-speed end, but 100K ECL compatible at the high-speed end The device has been fabricated with a 0.7㎛ BiCMOS gate array The fabricated chip shows the typical phase margin of 180 degrees and output data skew less than 470 ps at the high-speed end. And power dissipation is evaluated under 2.0W

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  Cite this article

[IEEE Style]

S. Lee and S. Kim, "A 155 Mb/s BiCMOS Multiplexer-Demultiplexer IC," The Journal of Korean Institute of Communications and Information Sciences, vol. 28, no. 1, pp. 47-53, 2003. DOI: .

[ACM Style]

Sang-hoon Lee and Seong-jeen Kim. 2003. A 155 Mb/s BiCMOS Multiplexer-Demultiplexer IC. The Journal of Korean Institute of Communications and Information Sciences, 28, 1, (2003), 47-53. DOI: .

[KICS Style]

Sang-hoon Lee and Seong-jeen Kim, "A 155 Mb/s BiCMOS Multiplexer-Demultiplexer IC," The Journal of Korean Institute of Communications and Information Sciences, vol. 28, no. 1, pp. 47-53, 1. 2003.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880