A Design on the A/D converter with architecture of Σ-Δ 


Vol. 28,  No. 1, pp. 14-23, Jan.  2003


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  Abstract

This thesis proposes a sigma-delta modulator architecture with 2 Ms/s data rate and 12 bit resolution A sigma-delta modulator has the features of oversampling and noise shaping With these features, it can be conneted with low resolution A/D converter to achieve higher resolution A/D converter Most previous researches have been concentrated on high resolution but low data rate applications, e.g audio applications But, in order to be applied to various applications such as wireless data communication, researches on sigma-delta modulator architecture for higher data rate are required The proposed sigma-delta modulator architecture has the sampling rate of 16 times Nyquist rate to achieve high data rate, and consists of a cascade of two 2nd order sigma-delta modulator to get relatively high resolution The experimental result shows that the proposed architecture achieves 12-bit resolution at 2 Ms/s data rate

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  Cite this article

[IEEE Style]

J. Yoon and J. Chong, "A Design on the A/D converter with architecture of Σ-Δ," The Journal of Korean Institute of Communications and Information Sciences, vol. 28, no. 1, pp. 14-23, 2003. DOI: .

[ACM Style]

Jeoung-Sig Yoon and Jong-Wha Chong. 2003. A Design on the A/D converter with architecture of Σ-Δ. The Journal of Korean Institute of Communications and Information Sciences, 28, 1, (2003), 14-23. DOI: .

[KICS Style]

Jeoung-Sig Yoon and Jong-Wha Chong, "A Design on the A/D converter with architecture of Σ-Δ," The Journal of Korean Institute of Communications and Information Sciences, vol. 28, no. 1, pp. 14-23, 1. 2003.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880