An Optimal SMT Processor Architecture for IPv4 Packet Routing 


Vol. 29,  No. 3, pp. 347-357, Mar.  2004


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  Abstract

Network systems have been developed 10 meet the high performance of forwarding packets and flexibility for providing various services. so network processor emerged. In order to improve the performance of network processors, fast external interface and special functional units have been used. Recently as an architectural method of improving performance, the SMT(Simultaneous MultiThreading) architecture is proposed, bur this architecture is difficult to implement due 10 its complexity. Therefore research for architectural optimization is needed to develop the SMT network processors. In this paper we analyze each functional units on performing network algorirhms and propose an optimized SMT network processor architecture.

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  Cite this article

[IEEE Style]

L. C. Bin, H. I. Pyo, C. J. Hyun, L. Y. Surk, "An Optimal SMT Processor Architecture for IPv4 Packet Routing," The Journal of Korean Institute of Communications and Information Sciences, vol. 29, no. 3, pp. 347-357, 2004. DOI: .

[ACM Style]

Lim Chung Bin, Hong In Pyo, Cho Jung Hyun, and Lee Yong Surk. 2004. An Optimal SMT Processor Architecture for IPv4 Packet Routing. The Journal of Korean Institute of Communications and Information Sciences, 29, 3, (2004), 347-357. DOI: .

[KICS Style]

Lim Chung Bin, Hong In Pyo, Cho Jung Hyun, Lee Yong Surk, "An Optimal SMT Processor Architecture for IPv4 Packet Routing," The Journal of Korean Institute of Communications and Information Sciences, vol. 29, no. 3, pp. 347-357, 3. 2004.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880