Design of an Optimal RSA Crypto-processor for Embedded Systems 


Vol. 29,  No. 4, pp. 447-457, Apr.  2004


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  Abstract

This paper proposes a RSA crypto-processor for embedded systems. The architecture of the RSA crypto-processor should be used relying on Big Montgomery algorithm, and is supported by configurable bit size. The RSA crypto-processor includes a RSA control signal generator, an optimal Big Montgomery processor(adder, multiplier). We use diverse arithmetic unit(adder, multiplier) algorithm. After we compared the various results, we selected the optimal arithmetic unit which can be connected with ARM core-processor. The RSA crypto-processor was implemented with Verilog HDL with top-down methodology, and it was verified by C language and Cadence Verilog-XL. The verified models were synthesized with a Hynix O.25um, CMOS standard cell library while using Synopsys Design Compiler. The RSA crypto-processor can operate at a clock speed of 51 MHz in this worst case conditions of 2.7V, 100℃ and has about 36,639 gates.

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  Cite this article

[IEEE Style]

S. Heo, M. Kim, Y. Lee, "Design of an Optimal RSA Crypto-processor for Embedded Systems," The Journal of Korean Institute of Communications and Information Sciences, vol. 29, no. 4, pp. 447-457, 2004. DOI: .

[ACM Style]

Seok-Won Heo, Moon-Gyung Kim, and Yong-Surk Lee. 2004. Design of an Optimal RSA Crypto-processor for Embedded Systems. The Journal of Korean Institute of Communications and Information Sciences, 29, 4, (2004), 447-457. DOI: .

[KICS Style]

Seok-Won Heo, Moon-Gyung Kim, Yong-Surk Lee, "Design of an Optimal RSA Crypto-processor for Embedded Systems," The Journal of Korean Institute of Communications and Information Sciences, vol. 29, no. 4, pp. 447-457, 4. 2004.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880