Study of Optimization for High Performance Adders 


Vol. 29,  No. 5, pp. 554-565, May  2004


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  Abstract

In this paper, we implement single cycle and multi cycle adders. We can compare area and time by using the implemented adders. The size of adders is 64, 128, 256-bits. The architecture of hybrid adders is that the carry-out of small adder groups can be interconnected by utilizing a carry propagate unit. The size of small adder groups is selected in three formats - 4, 8, 16-bits. These adders were implemented with Verilog HDL with top-down methodology, and they were verified by behavioral model. The verified models were synthesized with a Samsung O.35(um), 3.3(v) CMOS standard cell library while a using Synopsys Design Compiler. All adders were synthesized with group or ungroup. The optimized adder for a Crypto-processor included Smart Card IC is that a 64-bit RCA based on l6-bit CLA. All small adder groups in this optimized adder were synthesized with group. This adder can operate at a clock speed of 198 MHz and has about 967 gates. All adders can execute operations in this worst case conditions of 2.7 V, 85 ℃.

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  Cite this article

[IEEE Style]

S. Heo, M. Kim, Y. Lee, Y. Lee, "Study of Optimization for High Performance Adders," The Journal of Korean Institute of Communications and Information Sciences, vol. 29, no. 5, pp. 554-565, 2004. DOI: .

[ACM Style]

Seok-Won Heo, Moon-Gyung Kim, Yong-Joo Lee, and Yong-Surk Lee. 2004. Study of Optimization for High Performance Adders. The Journal of Korean Institute of Communications and Information Sciences, 29, 5, (2004), 554-565. DOI: .

[KICS Style]

Seok-Won Heo, Moon-Gyung Kim, Yong-Joo Lee, Yong-Surk Lee, "Study of Optimization for High Performance Adders," The Journal of Korean Institute of Communications and Information Sciences, vol. 29, no. 5, pp. 554-565, 5. 2004.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880