An Optimal Instruction Fetch Strategy for SMT Processors 


Vol. 27,  No. 5, pp. 512-521, May  2002


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  Abstract

Recently, conventional superscalar RiSC processors arrive their performance limit, and many researches on the next-generation architecture are concentrated on SMT(Simultaneous Multi-Threading). In SMT processors, multiple threads are executed simultaneously and share hardware resources dynamically. In this case, it is more important to supply instructions from multiple threads to processor core efficiently than ever. Because SMT architecture shows higher IPC(lnstructions per cycle) than superscalar architecture, performance is influenced by fetch bandwidth and the size of fetch queue. Moreover, to use TLP(Thread Level Parallelism) efficiently, fetch thread selection algorithm and fetch bandwidth for each selected threads must be carefully designed. Thus, in this paper, the performance values influenced by these factors are analyzed. Based on the results, an optimal instruction fetch strategy for SMT processors is proposed.

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  Cite this article

[IEEE Style]

I. Hong, B. Moon, M. Kim, Y. Lee, "An Optimal Instruction Fetch Strategy for SMT Processors," The Journal of Korean Institute of Communications and Information Sciences, vol. 27, no. 5, pp. 512-521, 2002. DOI: .

[ACM Style]

In-Pyo Hong, Byung-In Moon, Moon-Gyung Kim, and Yong-Surk Lee. 2002. An Optimal Instruction Fetch Strategy for SMT Processors. The Journal of Korean Institute of Communications and Information Sciences, 27, 5, (2002), 512-521. DOI: .

[KICS Style]

In-Pyo Hong, Byung-In Moon, Moon-Gyung Kim, Yong-Surk Lee, "An Optimal Instruction Fetch Strategy for SMT Processors," The Journal of Korean Institute of Communications and Information Sciences, vol. 27, no. 5, pp. 512-521, 5. 2002.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880