Full Data-rate Viterbi Decoder for DAB Receiver 


Vol. 27,  No. 6, pp. 601-609, Jun.  2002


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  Abstract

The efficient Viterbi decoder that supports full data-rate output of DAB system was proposed. Viterbi decoder consumes lots of computational load and should be designed to be fast specific hardware. In this paper, SST scheme was adopted for Viterbi decoder with pucturing to reduced the power consumption. Puncturing vector tables arc modified and re-arranged to be designed by a hardwired logic to save the system area. New re-scaling scheme which uses the fact that the difference of the maximum and minimum of the path metric values is bounded is proposed. The proposed re-scaling scheme optimizes the wordlength of path metric memory and greatly reduces the computational load for re-scaling by controlling MSB of path metric memory. Another saving of computation is done by proposed algorithm for branch metric calculation, which makes use of pre-calculated metric values. The designed Viterbi decoder was synthesized using SAMSUNG 0.3511 standard cell library and occupied small area and showed lower power consumption.

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  Cite this article

[IEEE Style]

H. Kim, W. Ko, J. Ryu, D. Youn, "Full Data-rate Viterbi Decoder for DAB Receiver," The Journal of Korean Institute of Communications and Information Sciences, vol. 27, no. 6, pp. 601-609, 2002. DOI: .

[ACM Style]

Hyo-Won Kim, Woo-Suk Ko, Joo-Hyun Ryu, and Dae-Hee Youn. 2002. Full Data-rate Viterbi Decoder for DAB Receiver. The Journal of Korean Institute of Communications and Information Sciences, 27, 6, (2002), 601-609. DOI: .

[KICS Style]

Hyo-Won Kim, Woo-Suk Ko, Joo-Hyun Ryu, Dae-Hee Youn, "Full Data-rate Viterbi Decoder for DAB Receiver," The Journal of Korean Institute of Communications and Information Sciences, vol. 27, no. 6, pp. 601-609, 6. 2002.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880