Design and Hardware Implementation of High-Speed Variable-Length RSA Cryptosystem 


Vol. 27,  No. 9, pp. 861-870, Sep.  2002


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  Abstract

In this paper, with targeting on the drawback of RSA of operation speed, a new 1024-bit RSA cryptosystem has been proposed and implemented in hardware to increase the operational speed and perform the variable-length encryption. The proposed cryptosystem mainly consists of the modular exponentiation part and the modular multiplication part. For the modular exponentiation, the RL-binary method, which performs squaring and modular multiplying in parallel, was improved, and then applied. And 4-stage CSA structure and radix-4 booth algorithm were applied to enhance the variable-length operation and reduce the number of partial product in modular multiplication arithmetic.
The proposed RSA cryptosystem which can calculate at most 1024 bits at a time was mapped into the integrated circuit using the Hynix Phantom Cell Library for Hynix 0.35㎛ 2-Poly 4-Metal CMOS process. Also, the result of software implementation,which had been programmed prior to the hardware research, has been used to verify the operation of the hardware system. The size of the result from the hardware implementation.

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  Cite this article

[IEEE Style]

J. Park, Y. Seo, D. Kim, "Design and Hardware Implementation of High-Speed Variable-Length RSA Cryptosystem," The Journal of Korean Institute of Communications and Information Sciences, vol. 27, no. 9, pp. 861-870, 2002. DOI: .

[ACM Style]

Jin-Young Park, Young-Ho Seo, and Dong-Wook Kim. 2002. Design and Hardware Implementation of High-Speed Variable-Length RSA Cryptosystem. The Journal of Korean Institute of Communications and Information Sciences, 27, 9, (2002), 861-870. DOI: .

[KICS Style]

Jin-Young Park, Young-Ho Seo, Dong-Wook Kim, "Design and Hardware Implementation of High-Speed Variable-Length RSA Cryptosystem," The Journal of Korean Institute of Communications and Information Sciences, vol. 27, no. 9, pp. 861-870, 9. 2002.