Giga-bps CMOS Clock and Data Recovery Circuit with a novel Adaptive Phase Detector 


Vol. 27,  No. 10, pp. 987-992, Oct.  2002


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  Abstract

In this paper, a new clock and data recovery circuit is proposed for the application of data communication systems requiring GHz-range clock signals. The circuit is suitable for recovering NRZ data which is widely used for high speed data transmission in GHz ranges. The high frequency jitter is one of major performance-limiting factors in PLL, particularly when NRZ data patterns are used. A novel phase detector is able to suppress this noise, and stable clock generation is achieved. Futhermore, the phase detector has an adaptive delay cell removing the dead zone problem and has the optimal characteristics for fast locking. The proposed circuit has a convenience structure that can be easily extended to multi-channels.The circuit is designed based on CMOS 0.25 ㎛ fabrication process and verified by measurement result.

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  Cite this article

[IEEE Style]

J. Lee, C. Lee, W. Choi, "Giga-bps CMOS Clock and Data Recovery Circuit with a novel Adaptive Phase Detector," The Journal of Korean Institute of Communications and Information Sciences, vol. 27, no. 10, pp. 987-992, 2002. DOI: .

[ACM Style]

Jae-Wook Lee, Cheon-O Lee, and Woo-Young Choi. 2002. Giga-bps CMOS Clock and Data Recovery Circuit with a novel Adaptive Phase Detector. The Journal of Korean Institute of Communications and Information Sciences, 27, 10, (2002), 987-992. DOI: .

[KICS Style]

Jae-Wook Lee, Cheon-O Lee, Woo-Young Choi, "Giga-bps CMOS Clock and Data Recovery Circuit with a novel Adaptive Phase Detector," The Journal of Korean Institute of Communications and Information Sciences, vol. 27, no. 10, pp. 987-992, 10. 2002.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880