A High-Speed Matched Filter for Searching Sychronization in DSSS Receiver 


Vol. 27,  No. 10, pp. 999-1007, Oct.  2002


PDF
  Abstract

In this paper, the operation of matched filter for searching initial synchronization in direct sequence spread spectrum receiver is studied. The implementation model of the matched filter by HDL (Hardware Description Language) is proposed. The model has an architecture based on parallelism and pipeline for fast processing, which includes circular buffer, multiplier, adder, and code look-up table. The performance of the model is analyzed and compared with the implementation by a conventional digital signal processor. It is implemented on a FPGA (Field Programmable Gate Array) and its operation is validated in a timing simulation result.

  Statistics
Cumulative Counts from November, 2022
Multiple requests among the same browser session are counted as one view. If you mouse over a chart, the values of data points will be shown.


  Cite this article

[IEEE Style]

M. Song, "A High-Speed Matched Filter for Searching Sychronization in DSSS Receiver," The Journal of Korean Institute of Communications and Information Sciences, vol. 27, no. 10, pp. 999-1007, 2002. DOI: .

[ACM Style]

Myong-Lyol Song. 2002. A High-Speed Matched Filter for Searching Sychronization in DSSS Receiver. The Journal of Korean Institute of Communications and Information Sciences, 27, 10, (2002), 999-1007. DOI: .

[KICS Style]

Myong-Lyol Song, "A High-Speed Matched Filter for Searching Sychronization in DSSS Receiver," The Journal of Korean Institute of Communications and Information Sciences, vol. 27, no. 10, pp. 999-1007, 10. 2002.

Search
(IN TITLE, AUTHOR, ABSTRACT,KEYWORDS)

Advanced Search ▼

POPULAR KEYWORDS
(TOP 10 KEYWORDS)

Recent Publications
(LAST 3 YEARS)






pISSN : 1226 - 4717
eISSN : 2287 - 3880