Hardware Implementation of Confidentiality and Integrity Algorithms for IMT - 2000 System 


Vol. 27,  No. 11, pp. 1028-1038, Nov.  2002


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  Abstract

In this paper, we designed the hardware of confidentiality and integrity algorithms for IMT-2000 system. The hardware is implemented to be able to calculate both confidentiality and integrity algorithms, and a pipelined KASUMI hardware is used for a core operator to achieve high operation frequency. And it has a PCI interface logic to communicate with a host system, and which makes our hardware to be easily applicable to practical environments. We tested our hardware on the FPGA board which we have designed, and its peak perform ace is about 330 Mbps encryption or decryption rate under 33 MHz clock frequency.

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  Cite this article

[IEEE Style]

Y. Choi, H. Kim, M. Kim, K. Chung, "Hardware Implementation of Confidentiality and Integrity Algorithms for IMT - 2000 System," The Journal of Korean Institute of Communications and Information Sciences, vol. 27, no. 11, pp. 1028-1038, 2002. DOI: .

[ACM Style]

Yong-je Choi, Ho-won Kim, Moo-seop Kim, and Kyo-il Chung. 2002. Hardware Implementation of Confidentiality and Integrity Algorithms for IMT - 2000 System. The Journal of Korean Institute of Communications and Information Sciences, 27, 11, (2002), 1028-1038. DOI: .

[KICS Style]

Yong-je Choi, Ho-won Kim, Moo-seop Kim, Kyo-il Chung, "Hardware Implementation of Confidentiality and Integrity Algorithms for IMT - 2000 System," The Journal of Korean Institute of Communications and Information Sciences, vol. 27, no. 11, pp. 1028-1038, 11. 2002.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880