Automatic Boundary Scan Circuits Generator for BIST 


Vol. 27,  No. 1, pp. 66-72, Jan.  2002


PDF
  Abstract

In this paper, we implemented the GenJTAG, a CAD tool, which generates a code of boundary scan circuit supporting a board level testing and a BIST(Built-ln Self Test) written in verilog-HDL. A boundary scan circuit code that supports users' own BIST instructions is generated based on the informations from the users. Most CAD tools hardly allow users to add their own BIST instructions because the generated code is described in gate-level. But the GenJTAG generates a behavioral boundary scan circuit code so users can easily make a change on the generated code

  Statistics
Cumulative Counts from November, 2022
Multiple requests among the same browser session are counted as one view. If you mouse over a chart, the values of data points will be shown.


  Cite this article

[IEEE Style]

S. Yang, J. Park, H. Chang, "Automatic Boundary Scan Circuits Generator for BIST," The Journal of Korean Institute of Communications and Information Sciences, vol. 27, no. 1, pp. 66-72, 2002. DOI: .

[ACM Style]

Sunwoong Yang, JaeHeung Park, and Hoon Chang. 2002. Automatic Boundary Scan Circuits Generator for BIST. The Journal of Korean Institute of Communications and Information Sciences, 27, 1, (2002), 66-72. DOI: .

[KICS Style]

Sunwoong Yang, JaeHeung Park, Hoon Chang, "Automatic Boundary Scan Circuits Generator for BIST," The Journal of Korean Institute of Communications and Information Sciences, vol. 27, no. 1, pp. 66-72, 1. 2002.

Search
(IN TITLE, AUTHOR, ABSTRACT,KEYWORDS)

Advanced Search ▼

POPULAR KEYWORDS
(TOP 10 KEYWORDS)

Recent Publications
(LAST 3 YEARS)






pISSN : 1226 - 4717
eISSN : 2287 - 3880