A VLSI Array Processor Architecture for High-Speed Processing of Full Search Block Matching Algorithm 


Vol. 27,  No. 4, pp. 364-370, Apr.  2002


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  Abstract

In this paper, we propose a VLSI array architecture for high speed processing of FBMA. First of all, the sequential FBMA is transformed into a single assignment code by using the index space expansion, and then the dependance graph is obtained from it. The two dimensional VLSI array is derived by projecting the dependance graph along the optimal direction. Since the candidate blocks in the search range are overlapped with columns as well as rows, the processing elements of the VLSI array are designed to reuse the overlapped data. As the results, the number of data inputs is reduced so that the processing performance is improved. The proposed VLSI array has (N^2+1) ×(2p+ 1) processing elements and (N+2p) input ports where N is the block size and p is the maximum search range. The computation time of the first reference block is (N^2+2(p+ 1)N+6p) , and the block pipeline period is (3N+4p-1).

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  Cite this article

[IEEE Style]

S. Lee and C. Woo, "A VLSI Array Processor Architecture for High-Speed Processing of Full Search Block Matching Algorithm," The Journal of Korean Institute of Communications and Information Sciences, vol. 27, no. 4, pp. 364-370, 2002. DOI: .

[ACM Style]

Su-jin Lee and Chong-ho Woo. 2002. A VLSI Array Processor Architecture for High-Speed Processing of Full Search Block Matching Algorithm. The Journal of Korean Institute of Communications and Information Sciences, 27, 4, (2002), 364-370. DOI: .

[KICS Style]

Su-jin Lee and Chong-ho Woo, "A VLSI Array Processor Architecture for High-Speed Processing of Full Search Block Matching Algorithm," The Journal of Korean Institute of Communications and Information Sciences, vol. 27, no. 4, pp. 364-370, 4. 2002.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880