FPGA-based One-Chip Architecture and Design of Real-time Video CODEC with Embedded Blind Watermarking 


Vol. 29,  No. 8, pp. 1113-1124, Aug.  2004


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  Abstract

In this paper, we proposed a hardware(H/W) structure which can compress and reconstruct the input image in ical time operation and implemented it into a FPGA platform using VHDL(VHSIC Hardware Description Language) All the image processing element to process both compression and reconstruction in a FPGA were considered each of them was mapped into H/W with the efficient structure for FPGA We used the DWT(discrete wavelet transform) which transforms the data from spatial domain to the frequency domain, because use considered the motion JPE2000 as the application The implemented H/W is separated to both the data path part and the control part The data path part consisted of the image processing blocks and the data processing blocks The image processing blocks consisted of the DWT Kernel of the filtering by DWT, Quantizer/Huffman Encoder, Inverse Adder/Buffer for adding the low frequency coefficient to the high frequency one in the inverse DWT operation, and Huffman Decoder Also there existed the interface blocks for communicating with the external application environments and the timing blocks for buffering between the internal blocks The global operations of the designed H/W are the image compression and the reconstruction, and it is operated by the unit of a field synchronized with the A/D converter The implemented H/W used the 69％(16980) LAB(Logic Array Block) and 9％(28352) ESB(Embedded System Block) in the APEX20KC600CB6520-7 FPGA chip of ALTERA, and stably operated in the 70㎒ clock frequency So we verified the real time operation of 60 fields/sec(30 frames/sec).

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  Cite this article

[IEEE Style]

Y. Seo, D. Kim, J. Yoo, D. Kim, "FPGA-based One-Chip Architecture and Design of Real-time Video CODEC with Embedded Blind Watermarking," The Journal of Korean Institute of Communications and Information Sciences, vol. 29, no. 8, pp. 1113-1124, 2004. DOI: .

[ACM Style]

Young-Ho Seo, Dae-Gyoung Kim, Ji-Sang Yoo, and Dong-Wook Kim. 2004. FPGA-based One-Chip Architecture and Design of Real-time Video CODEC with Embedded Blind Watermarking. The Journal of Korean Institute of Communications and Information Sciences, 29, 8, (2004), 1113-1124. DOI: .

[KICS Style]

Young-Ho Seo, Dae-Gyoung Kim, Ji-Sang Yoo, Dong-Wook Kim, "FPGA-based One-Chip Architecture and Design of Real-time Video CODEC with Embedded Blind Watermarking," The Journal of Korean Institute of Communications and Information Sciences, vol. 29, no. 8, pp. 1113-1124, 8. 2004.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880