On a High-speed Implementation of LILI-Ⅱ Stream Cipher 


Vol. 29,  No. 8, pp. 1210-1217, Aug.  2004


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  Abstract

LILI-Ⅱ stream cipher is an upgraded version of the LILI-128, one of candidates in NESSIE Since the algorithm is a clock-controlled, the speed of the key-stream data is degraded structurally in a clock-synchronized hardware logic design Accordingly, this paper proposes a 4-bit parallel LFSR, where each register bit includes four variable data routines for feedback on shifting within the LFSR Furthermore, the timing of the proposed design is simulated suing a Max+plus II from the ALTERA Co, the logic circuit is implemented for an FPGA device (EPF10K20RC240-3), and apply to the Lucent ASIC device (LV160C0.13μm CMOS & 1.5V technology), and it could achieve a throughput of about 500 Mbps with a 0.13μm semiconductor for maximum path delay below 1.8ns Finally, we propose the m-parallel implementation of LILI-II, throughput with 4,8 or 16 Gbps(m=8,16 or 32).

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  Cite this article

[IEEE Style]

H. Lee and S. Moon, "On a High-speed Implementation of LILI-Ⅱ Stream Cipher," The Journal of Korean Institute of Communications and Information Sciences, vol. 29, no. 8, pp. 1210-1217, 2004. DOI: .

[ACM Style]

Hoon-Jae Lee and Sang-Jae Moon. 2004. On a High-speed Implementation of LILI-Ⅱ Stream Cipher. The Journal of Korean Institute of Communications and Information Sciences, 29, 8, (2004), 1210-1217. DOI: .

[KICS Style]

Hoon-Jae Lee and Sang-Jae Moon, "On a High-speed Implementation of LILI-Ⅱ Stream Cipher," The Journal of Korean Institute of Communications and Information Sciences, vol. 29, no. 8, pp. 1210-1217, 8. 2004.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880