Design of Receiver Architecture for HomePNA 2.0 Modem 


Vol. 29,  No. 9, pp. 991-997, Sep.  2004


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  Abstract

In this paper, we propose the architecture of modem receiver to fabricate HomePNA 2.0 chip. HomePNA suffers from inferior channel because of bridge tap, the effect of amateur HAM band and so on. To transfer data over such channel, HomePNA 2.0 uses training sequence to equalize channel and uses FD-QAM optionally as modulation method. So modem receiver demodulate QAM based signal and needs optimum architecture that fully uses these transmission feature. As a result of research, we define 2 mode function of modem receiver depending on TX/RX state. In this paper, particularly, we show the algorithm of equalizer, carrier phase recovery and frame synchromzationblock and propose architecture that improve the performance of channel equalization and is stable in operation. In the end, we estimate the performance of proposed HomePNA2.0 modem receiver over HomePNA TEST LOOP using SPW program.

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  Cite this article

[IEEE Style]

S. Choi and J. Kim, "Design of Receiver Architecture for HomePNA 2.0 Modem," The Journal of Korean Institute of Communications and Information Sciences, vol. 29, no. 9, pp. 991-997, 2004. DOI: .

[ACM Style]

Sung-woo Choi and Jong-won Kim. 2004. Design of Receiver Architecture for HomePNA 2.0 Modem. The Journal of Korean Institute of Communications and Information Sciences, 29, 9, (2004), 991-997. DOI: .

[KICS Style]

Sung-woo Choi and Jong-won Kim, "Design of Receiver Architecture for HomePNA 2.0 Modem," The Journal of Korean Institute of Communications and Information Sciences, vol. 29, no. 9, pp. 991-997, 9. 2004.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880