A Design of High Performance Parallel CRC Generator 


Vol. 29,  No. 9, pp. 1101-1107, Sep.  2004


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  Abstract

This paper presents an optimization algorithm and technique for designing parallel Cyclic Redundancy Check (CRC) circuit, which is most widely adopted for error detection A new heuristic algorithm is developed to find as many shared terms as possible, thus eventually to minimize the number and level of the exclusive-or logic blocks in parallel CRC circuits. 16-bit and 32-bit CRC generators are designed with different types of Programmable Logic Devices, and it has been found that our new algorithm and architecture significantly reduce the delay.

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  Cite this article

[IEEE Style]

H. Yi, S. Park, P. Min, C. Park, "A Design of High Performance Parallel CRC Generator," The Journal of Korean Institute of Communications and Information Sciences, vol. 29, no. 9, pp. 1101-1107, 2004. DOI: .

[ACM Style]

Hyunbean Yi, Sungju Park, Pyoungwoo Min, and Changwon Park. 2004. A Design of High Performance Parallel CRC Generator. The Journal of Korean Institute of Communications and Information Sciences, 29, 9, (2004), 1101-1107. DOI: .

[KICS Style]

Hyunbean Yi, Sungju Park, Pyoungwoo Min, Changwon Park, "A Design of High Performance Parallel CRC Generator," The Journal of Korean Institute of Communications and Information Sciences, vol. 29, no. 9, pp. 1101-1107, 9. 2004.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880