Implementation of MPEG/Audio Decoder based on RISC Processor with Minimized DSP Accelerator 


Vol. 29,  No. 12, pp. 1617-1622, Dec.  2004


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  Abstract

MPEG/Audio decoder for mobile multimedia systems requires low power consumption. Implementations of AV decoder using a single RISC processor often need high power consumption owing to cash-miss in case of insufficient cash memory. In this paper, we present a MPEG/Audio decoder for mobile handset applications and implement it on a RISC processor embedding a minimized DSP accelerator. Audio decoding algorithm is splitted into two parts, computation intensive and control intensive parts. Those parts are, respectively, allocated to DSP and RISC core, which are designed to run in parallel to increase the processing efficiency. The proposed system implements MP3 and AAC decoders at 17MHz and 24MHz clocks, which are reductions of 48% and 40% of complexities in comparison with implementations on a single RISC processor. The proposed method is adequate for mobile multimedia applications with insufficient cash memory.

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  Cite this article

[IEEE Style]

K. H. Bang, K. S. Lee, Y. C. Park, D. H. Youn, "Implementation of MPEG/Audio Decoder based on RISC Processor with Minimized DSP Accelerator," The Journal of Korean Institute of Communications and Information Sciences, vol. 29, no. 12, pp. 1617-1622, 2004. DOI: .

[ACM Style]

Kyoung Ho Bang, Keun Sup Lee, Young Cheol Park, and Dae Hee Youn. 2004. Implementation of MPEG/Audio Decoder based on RISC Processor with Minimized DSP Accelerator. The Journal of Korean Institute of Communications and Information Sciences, 29, 12, (2004), 1617-1622. DOI: .

[KICS Style]

Kyoung Ho Bang, Keun Sup Lee, Young Cheol Park, Dae Hee Youn, "Implementation of MPEG/Audio Decoder based on RISC Processor with Minimized DSP Accelerator," The Journal of Korean Institute of Communications and Information Sciences, vol. 29, no. 12, pp. 1617-1622, 12. 2004.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880