Efficient Radix-4 Systolic VLSI Architecture for RSA Public-key Cryptosystem 


Vol. 29,  No. 12, pp. 1739-1747, Dec.  2004


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  Abstract

In this paper, an efficient radix-4 systolic VLSI architecture for RSA public-key cryptosystem is proposed. Due to the simple operation of iterations and the efficient systolic mapping, the proposed architecture computes an n-bit modular exponentiation in n²clock cycles since two modular multiplications for M₁and P₁in each exponentiation process are interleaved, so that the hardware is fully utilized. We encode the exponent using Radix-4 SD (Signed Digit) number system to reduce the number of modular multiplications for RSA cryptography. Therefore about 20% of NZ (non-zero) digits in the exponent are reduced. Compared to conventional approaches, the proposed architecture shows shorter period to complete the RSA while requiring relatively less hardware resources. The proposed RSA architecture based on the modified Montgomery algorithm has locality, regularity, and scalability suitable for VLSI implementation.

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  Cite this article

[IEEE Style]

T. Park, "Efficient Radix-4 Systolic VLSI Architecture for RSA Public-key Cryptosystem," The Journal of Korean Institute of Communications and Information Sciences, vol. 29, no. 12, pp. 1739-1747, 2004. DOI: .

[ACM Style]

Taegeun Park. 2004. Efficient Radix-4 Systolic VLSI Architecture for RSA Public-key Cryptosystem. The Journal of Korean Institute of Communications and Information Sciences, 29, 12, (2004), 1739-1747. DOI: .

[KICS Style]

Taegeun Park, "Efficient Radix-4 Systolic VLSI Architecture for RSA Public-key Cryptosystem," The Journal of Korean Institute of Communications and Information Sciences, vol. 29, no. 12, pp. 1739-1747, 12. 2004.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880