Open-Loop Pipeline ADC Design Techniques for High Speed & Low Power Consumption 


Vol. 30,  No. 1, pp. 104-112, Jan.  2005


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  Abstract

Some design techniques for high speed and low power pipelined 8-bit ADC are described To perform high-speed operation with relatively low power consumption, open loop architecture is adopted. while closed loop architecture (with MDAC) is used in conventional plpelme ADC A distributed track and hold amplifier and a cascading structure are also adopted to increase the sampling rate. To reduce the power consumption and the we area, the number of amplifiers in each stage are optimized and reduced with proposed zero-crossing point generation method. At 500-㎒ sampling rate. simulation results show that the power consumption is 210mW including digital logic with 1.8V power supply And the targeted ADC achieves ENOB of about 8-bit with input frequency up to 200-㎒ and input range of 1.2Vpp (Differential). The ADC is designed using a 0.18㎛ 6-Metal i-Poly CMOS process and occupies an area of 9OO㎛×500㎛.

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  Cite this article

[IEEE Style]

S. Kim, Y. Kim, J. Youn, S. Lim, S. Kang, S. Kim, "Open-Loop Pipeline ADC Design Techniques for High Speed & Low Power Consumption," The Journal of Korean Institute of Communications and Information Sciences, vol. 30, no. 1, pp. 104-112, 2005. DOI: .

[ACM Style]

Shinhoo Kim, Yunjeong Kim, Jaeyoun Youn, Shin-ll Lim, Sung-Mo Kang, and Suki Kim. 2005. Open-Loop Pipeline ADC Design Techniques for High Speed & Low Power Consumption. The Journal of Korean Institute of Communications and Information Sciences, 30, 1, (2005), 104-112. DOI: .

[KICS Style]

Shinhoo Kim, Yunjeong Kim, Jaeyoun Youn, Shin-ll Lim, Sung-Mo Kang, Suki Kim, "Open-Loop Pipeline ADC Design Techniques for High Speed & Low Power Consumption," The Journal of Korean Institute of Communications and Information Sciences, vol. 30, no. 1, pp. 104-112, 1. 2005.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880