DESIGN OF A HIGH-THROUGHPUT VITERBI DECODER 


Vol. 30,  No. 2, pp. 20-25, Feb.  2005


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  Abstract

A high performance Viterbi decoder is designed using modified register exchange scheme and block decoding method. The elimination of the trace-back operation reduces the operation cycles to determine the merging state and the amount of memory. The Viterbi decoder has low latency, efficient memory organization, and low hardware complexity compared with other Viterbi decoding methods in block decoding architectures. The elimination of trace-back also reduces the power consumption for finding the merging state and the access to the memory. The proposed decoder can be designed with emphasis on either efficient memory or low latency. Also, it has a scalable structure so that the complexity of the hardware and the throughput are adjusted by changing a few design parameters before synthesis.

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  Cite this article

[IEEE Style]

T. Kim and C. Lee, "DESIGN OF A HIGH-THROUGHPUT VITERBI DECODER," The Journal of Korean Institute of Communications and Information Sciences, vol. 30, no. 2, pp. 20-25, 2005. DOI: .

[ACM Style]

Tae-Jin Kim and Chanho Lee. 2005. DESIGN OF A HIGH-THROUGHPUT VITERBI DECODER. The Journal of Korean Institute of Communications and Information Sciences, 30, 2, (2005), 20-25. DOI: .

[KICS Style]

Tae-Jin Kim and Chanho Lee, "DESIGN OF A HIGH-THROUGHPUT VITERBI DECODER," The Journal of Korean Institute of Communications and Information Sciences, vol. 30, no. 2, pp. 20-25, 2. 2005.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880