Parallel Feedback Oscillator for Strong Harmonics Suppression and Frequency Doubler 


Vol. 30,  No. 2, pp. 122-128, Feb.  2005


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  Abstract

In this paper, a low noise parallel feedback oscillator for harmonic suppression and a frequency doubler are designed and implemented. As the fundamental signal of the oscillator for frequency doubling is extracted between the dielectric resonator (DR) filter and the gate device of the active device, the undesired harmonics at the output of the oscillator is remarkably suppressed. The fundamental signal of the oscillator for frequency doubling directly feeds to the frequency doubler without an additional band pass filter for harmonic suppression. The second harmonic suppression of -47.7 dBc at the oscillator output is achieved, while the fundamental suppression of -37.5 dBc at the doubler output is obtained. The phase noise characteristics are -80.3 dBc/Hz and -93.5 dBc/Hz at the offset frequency of 10 KHz and 100 KHz from the carrier, respectively.

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  Cite this article

[IEEE Style]

K. Lee, J. Ko, Y. Kim, "Parallel Feedback Oscillator for Strong Harmonics Suppression and Frequency Doubler," The Journal of Korean Institute of Communications and Information Sciences, vol. 30, no. 2, pp. 122-128, 2005. DOI: .

[ACM Style]

Kun-Joon Lee, Jung-Pil Ko, and Young-Sik Kim. 2005. Parallel Feedback Oscillator for Strong Harmonics Suppression and Frequency Doubler. The Journal of Korean Institute of Communications and Information Sciences, 30, 2, (2005), 122-128. DOI: .

[KICS Style]

Kun-Joon Lee, Jung-Pil Ko, Young-Sik Kim, "Parallel Feedback Oscillator for Strong Harmonics Suppression and Frequency Doubler," The Journal of Korean Institute of Communications and Information Sciences, vol. 30, no. 2, pp. 122-128, 2. 2005.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880