Host Interface Design for TCP/IP Hardware Accelerator 


Vol. 30,  No. 2, pp. 1-10, Feb.  2005


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  Abstract

TCP/IP protocols have been implemented in software program running on CPU in end systems. As the increased demand of fast protocol processing, it is required to implement the protocols in hardware, and Host Interface is responsible for communication between external CPU and the hardware blocks of TCP/IP implementation. The Host Interface follows AMBA AHB specification for the communication with external world. For control flow, the Host Interface behaves as a slave of AMBA AHB. Using internal Command/Status Registers, the Host Interface receives commands from CPU and transfers hardware status and header information to CPU. On the other hand, the Host Interface behaves as a master for data flow. Data flow has two directions, Receive Flow and Transmit Flow. In Receive Flow, using internal RxFIFO, the Host Interface reads data from UDP FIFO or TCP buffer and transfers data to external RAM for CPU to read. For Transmit Flow, the Host Interface reads data from external RAM and transfers data to UDP buffer or TCP buffer through internal
TxFIFO. TCP/IP hardware blocks generate packets using the data and transmit. Buffer Descriptor is one of the Command/Status Registers, and the information stored in Buffer Descriptor is used for external RAM access. Several testcases are designed to verify TCP/IP functions. The Host Interface is synthesized using the 0.18
micron technology, and it results in 173 K gates including the Command/Status Registers and internal FIFOs.

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  Cite this article

[IEEE Style]

Y. Jung and H. Lim, "Host Interface Design for TCP/IP Hardware Accelerator," The Journal of Korean Institute of Communications and Information Sciences, vol. 30, no. 2, pp. 1-10, 2005. DOI: .

[ACM Style]

Yeojin Jung and Hyesook Lim. 2005. Host Interface Design for TCP/IP Hardware Accelerator. The Journal of Korean Institute of Communications and Information Sciences, 30, 2, (2005), 1-10. DOI: .

[KICS Style]

Yeojin Jung and Hyesook Lim, "Host Interface Design for TCP/IP Hardware Accelerator," The Journal of Korean Institute of Communications and Information Sciences, vol. 30, no. 2, pp. 1-10, 2. 2005.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880