Advanced On-Chip Debugging Unit Design for JTAG-based SoC 


Vol. 30,  No. 3, pp. 226-232, Mar.  2005


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  Abstract

An on-chip debugging unit is proposed aiming performance enhancement of JTAG-based SoC systems. The proposed unit comprises a JTAG module and a core breaker. The IEEE 1149.1 standard has been modified and applied to the new JTAG module. The proposed unit eliminates redundant clock cycles included in the TAP command execution stage. TAP execution commands are repeatedly issued to perform debugging of complicated SoC systems. Simulation on the proposed unit shows some 14% performance enhancement and 50% gate count reduction compared to the conventional ones.

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  Cite this article

[IEEE Style]

Y. s. Yun, K. h. Ryoo, Y. d. Kim, S. k. Han, Y. g. You, "Advanced On-Chip Debugging Unit Design for JTAG-based SoC," The Journal of Korean Institute of Communications and Information Sciences, vol. 30, no. 3, pp. 226-232, 2005. DOI: .

[ACM Style]

Yeon sang Yun, Kwang hyun Ryoo, Yong dae Kim, Seon kyoung Han, and Young gap You. 2005. Advanced On-Chip Debugging Unit Design for JTAG-based SoC. The Journal of Korean Institute of Communications and Information Sciences, 30, 3, (2005), 226-232. DOI: .

[KICS Style]

Yeon sang Yun, Kwang hyun Ryoo, Yong dae Kim, Seon kyoung Han, Young gap You, "Advanced On-Chip Debugging Unit Design for JTAG-based SoC," The Journal of Korean Institute of Communications and Information Sciences, vol. 30, no. 3, pp. 226-232, 3. 2005.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880