Complexity Analysis of a VHDL Implementation of the Bit-Serial Reed-Solomon Encoder 


Vol. 30,  No. 3, pp. 64-68, Mar.  2005


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  Abstract

Reed-Solomon code is one of the most versatile channel codes. The encoder can be implemented with two famous structures: ordinary and bit-serial. The ordinary encoder is generally known to be complex and fast, while the bit-serial encoder is simple and not so fast. However, it may not be true for a longer codeword length at least in VHDL implementation. In this letter, it is shown that, when the encoder is implemented with VHDL, the number of logic gates of the bit-serial encoder might be larger than that of the ordinary encoder if the dual basis conversion table has to be used. It is also shown that the encoding speeds of the two VHDL implemented encoders are exactly same.

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  Cite this article

[IEEE Style]

S. h. Back, I. h. Song, J. s. Bae, "Complexity Analysis of a VHDL Implementation of the Bit-Serial Reed-Solomon Encoder," The Journal of Korean Institute of Communications and Information Sciences, vol. 30, no. 3, pp. 64-68, 2005. DOI: .

[ACM Style]

Seung hun Back, Iick ho Song, and Jin soo Bae. 2005. Complexity Analysis of a VHDL Implementation of the Bit-Serial Reed-Solomon Encoder. The Journal of Korean Institute of Communications and Information Sciences, 30, 3, (2005), 64-68. DOI: .

[KICS Style]

Seung hun Back, Iick ho Song, Jin soo Bae, "Complexity Analysis of a VHDL Implementation of the Bit-Serial Reed-Solomon Encoder," The Journal of Korean Institute of Communications and Information Sciences, vol. 30, no. 3, pp. 64-68, 3. 2005.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880