SRAM Reuse Design and Verification by Redundancy Memory 


Vol. 30,  No. 4, pp. 328-335, Apr.  2005


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  Abstract

In this paper, built-in self-repair(BISR) is proposed for semiconductor memories. BISR is consisted of BIST (Buit-in self-test) and BIRU(Built-In Remapping Uint). BIST circuits are required not only to detect the presence of faults but also to specify their locations for repair. The memory rows are virtually divided into row blocks and reconfiguration is performed at the row block level instead of the traditional row level. According to the experimental result, we can verify algorithm for replacement of faulty cell.

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  Cite this article

[IEEE Style]

E. s. Shim and H. Chang, "SRAM Reuse Design and Verification by Redundancy Memory," The Journal of Korean Institute of Communications and Information Sciences, vol. 30, no. 4, pp. 328-335, 2005. DOI: .

[ACM Style]

Eun sung Shim and Hoon Chang. 2005. SRAM Reuse Design and Verification by Redundancy Memory. The Journal of Korean Institute of Communications and Information Sciences, 30, 4, (2005), 328-335. DOI: .

[KICS Style]

Eun sung Shim and Hoon Chang, "SRAM Reuse Design and Verification by Redundancy Memory," The Journal of Korean Institute of Communications and Information Sciences, vol. 30, no. 4, pp. 328-335, 4. 2005.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880