VLSI architecture design of CAVLC entropy encoder/decoder for H.264/AVC 


Vol. 30,  No. 5, pp. 371-381, May  2005


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  Abstract

In this paper, we propose an advanced hardware architecture for the CAVLC entropy encoder/decoder engine for real time video compression. The CAVLC (Context-based Adaptive Variable Length Coding) is a lossless compression method in H.264/AVC and it has high compression efficiency but has computational complexity. The reference memory size is optimized using partitioned storing method and memory reuse method which are based on partiality of memory referencing. We choose the hardware architecture which has the most suitable one in several encoder/decoder architectures for the mobile devices and improve its performance using parallel processing. The proposed architecture has been verified by ARM-interfaced emulation board using Altera Excalibur and also synthesized on Samsung 0.18 um CMOS technology. The synthesis result shows that the encoder can process about 300 CIF frames/s at 150MHz and the decoder can process about 250 CIF frames/s at 140Mhz. The hardware architectures are being used as core modules when implementing a complete H.264/AVC video encoder/decoder chip for real-time multimedia application.

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  Cite this article

[IEEE Style]

D. Lee and Y. Jeong, "VLSI architecture design of CAVLC entropy encoder/decoder for H.264/AVC," The Journal of Korean Institute of Communications and Information Sciences, vol. 30, no. 5, pp. 371-381, 2005. DOI: .

[ACM Style]

Dae-joon Lee and Yong-jin Jeong. 2005. VLSI architecture design of CAVLC entropy encoder/decoder for H.264/AVC. The Journal of Korean Institute of Communications and Information Sciences, 30, 5, (2005), 371-381. DOI: .

[KICS Style]

Dae-joon Lee and Yong-jin Jeong, "VLSI architecture design of CAVLC entropy encoder/decoder for H.264/AVC," The Journal of Korean Institute of Communications and Information Sciences, vol. 30, no. 5, pp. 371-381, 5. 2005.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880