Construction of an Automatic Generation System of Embedded Processor Cores 


Vol. 30,  No. 6, pp. 526-534, Jun.  2005


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  Abstract

This paper presents the structure and function of the system which automatically generates embedded processor cores using the SMDL. Accepting processor description in the SDML, the proposed system generates the processor core, consisting of the pipelined datapath and memory modules together with their control unit. The generated cores support muti-cycle instructions for proper handling of memory accesses, and resolve pipeline hazards encountered in the pipelined processors. Experimental results show the functional accuracy of the generated cores.

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  Cite this article

[IEEE Style]

J. Cho, Y. You, S. Hwang, "Construction of an Automatic Generation System of Embedded Processor Cores," The Journal of Korean Institute of Communications and Information Sciences, vol. 30, no. 6, pp. 526-534, 2005. DOI: .

[ACM Style]

Jae-Bum Cho, Yong-Ho You, and Sun-Young Hwang. 2005. Construction of an Automatic Generation System of Embedded Processor Cores. The Journal of Korean Institute of Communications and Information Sciences, 30, 6, (2005), 526-534. DOI: .

[KICS Style]

Jae-Bum Cho, Yong-Ho You, Sun-Young Hwang, "Construction of an Automatic Generation System of Embedded Processor Cores," The Journal of Korean Institute of Communications and Information Sciences, vol. 30, no. 6, pp. 526-534, 6. 2005.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880