FPGA Design of Open-Loop Frame Prediction Processor for Scalable Video Coding 


Vol. 31,  No. 5, pp. 534-539, May  2006


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  Abstract

In this paper, we propose a new frame prediction filtering technique and a hardware(H/W) architecture for scalable video coding. We try to evaluate MCTF(motion compensated temporal filtering) and hierarchical B-picture which are a technique for eliminate correlation between video frames. Since the techniques correspond to non-causal system in time, these have fundamental defects which are long latency time and large size of frame buffer. We propose a new architecture to be efficiently implemented by reconfiguring non-causal system to causal system. We use the property of a repetitive arithmetic and propose a new frame prediction filtering cell(FPFC). By expanding FPFC we reconfigure the whole arithmetic architecture. After the operational sequence of arithmetic is analyzed in detail and the causality is imposed to implement in hardware, the unit cell is optimized. A new FPFC kernel was organized as simple as possible by repeatedly arranging the unit cells and a FPFC processor is realized for scalable video coding.

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  Cite this article

[IEEE Style]

Y. Seo, "FPGA Design of Open-Loop Frame Prediction Processor for Scalable Video Coding," The Journal of Korean Institute of Communications and Information Sciences, vol. 31, no. 5, pp. 534-539, 2006. DOI: .

[ACM Style]

Young-Ho Seo. 2006. FPGA Design of Open-Loop Frame Prediction Processor for Scalable Video Coding. The Journal of Korean Institute of Communications and Information Sciences, 31, 5, (2006), 534-539. DOI: .

[KICS Style]

Young-Ho Seo, "FPGA Design of Open-Loop Frame Prediction Processor for Scalable Video Coding," The Journal of Korean Institute of Communications and Information Sciences, vol. 31, no. 5, pp. 534-539, 5. 2006.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880