A Design of AES-based CCMP core for IEEE 802.11i Wireless LAN Security 


Vol. 31,  No. 6, pp. 640-647, Jun.  2006


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  Abstract

This paper describes a design of AES-based CCMP(Counter mode with CBC-MAC Protocol) core for IEEE 802.11i wireless LAN security. To maximize the performance of CCMP core, two AES cores are used, one is the counter mode for data confidentiality and the other is the CBC mode for authentication and data integrity. The S-box that requires the largest hardware in AES core is implemented using composite field arithmetic, and the gate count is reduced by about 27% compared with conventional LUT(Lookup Table)-based design. The CCMP core was verified using Excalibur SoC kit, and a MPW chip is fabricated using a 0.35-um CMOS standard cell technology. The test results show that all the function of the fabricated chip works correctly. The CCMP processor has 17,000 gates, and the estimated throughput is about 353-Mbps at 116-MHz@3.3V, satisfying 54-Mbps data rate of the IEEE 802.11a and 802.11g specifications.

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  Cite this article

[IEEE Style]

S. Hwang, J. Kim, K. Shin, "A Design of AES-based CCMP core for IEEE 802.11i Wireless LAN Security," The Journal of Korean Institute of Communications and Information Sciences, vol. 31, no. 6, pp. 640-647, 2006. DOI: .

[ACM Style]

Seok-Ki Hwang, Jong-Whan Kim, and Kyung-Wook Shin. 2006. A Design of AES-based CCMP core for IEEE 802.11i Wireless LAN Security. The Journal of Korean Institute of Communications and Information Sciences, 31, 6, (2006), 640-647. DOI: .

[KICS Style]

Seok-Ki Hwang, Jong-Whan Kim, Kyung-Wook Shin, "A Design of AES-based CCMP core for IEEE 802.11i Wireless LAN Security," The Journal of Korean Institute of Communications and Information Sciences, vol. 31, no. 6, pp. 640-647, 6. 2006.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880