Performance Comparison of DCT Algorithm Implementations Based on Hardware Architecture 


Vol. 31,  No. 6, pp. 637-644, Jun.  2006


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  Abstract

This paper presents performance and implementation comparisons of standard and fast DCT algorithms that are commonly used for subband filter bank in MPEG audio coders. The comparison is made according to the architectural difference of the implementation hardware. Fast DCT algorithms are known to have much less computational complexity than the standard method that involves computing a vector dot product of cosine coefficient. But, due to structural irregularity, fast DCT algorithms require extra cycles to generate the addresses for operands and to realign interim data. When algorithms are implemented using DSP processors that provide special operations such as single-cycle MAC (multiply-accumulate), zero-overhead nested loop, the standard algorithm is more advantageous than the fast algorithms. Also, in case of the finite-precision processing, the error performance of the standard method is far superior to that of the fast algorithms. In this paper, truncation errors and algorithmic suitability are analyzed and implementation results are provided to support the analysis.

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  Cite this article

[IEEE Style]

J. Lee, Y. Park, D. H. Youn, "Performance Comparison of DCT Algorithm Implementations Based on Hardware Architecture," The Journal of Korean Institute of Communications and Information Sciences, vol. 31, no. 6, pp. 637-644, 2006. DOI: .

[ACM Style]

Jae-Seong Lee, Young-Cheol Park, and Dae Hee Youn. 2006. Performance Comparison of DCT Algorithm Implementations Based on Hardware Architecture. The Journal of Korean Institute of Communications and Information Sciences, 31, 6, (2006), 637-644. DOI: .

[KICS Style]

Jae-Seong Lee, Young-Cheol Park, Dae Hee Youn, "Performance Comparison of DCT Algorithm Implementations Based on Hardware Architecture," The Journal of Korean Institute of Communications and Information Sciences, vol. 31, no. 6, pp. 637-644, 6. 2006.