Design of a Variable Shortened and Punctured RS Decoder 


Vol. 31,  No. 8, pp. 763-770, Aug.  2006


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  Abstract

In this paper, a variable Reed-Solomon(RS) decoder with erasure decoding functionality is designed based on the modified Euclid's algorithm(MEA). The variability of the decoder is implemented through shortening and puncturing based on the RS(124, 108, 8) code, other than the primitive RS(255, 239, 8) code. This leads to shortening the decoding latency. The decoder performs 4-step pipelined operation, where each step is designed to be clocked by an independent clock. Thus by using a faster clock for the MEA block, the complexity and the decoding latency can be reduced. It can support both continuous- and burst-mode decoding. It has been designed in VHDL and synthesized in an FPGA chip, consuming 3,717 logic cells and 2,048-bit memories. The maximum decoding throughput is 33 MByte/sec.

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  Cite this article

[IEEE Style]

M. K. Song, M. H. Kong, M. S. Lim, "Design of a Variable Shortened and Punctured RS Decoder," The Journal of Korean Institute of Communications and Information Sciences, vol. 31, no. 8, pp. 763-770, 2006. DOI: .

[ACM Style]

Moon Kyou Song, Min Han Kong, and Myoung Seob Lim. 2006. Design of a Variable Shortened and Punctured RS Decoder. The Journal of Korean Institute of Communications and Information Sciences, 31, 8, (2006), 763-770. DOI: .

[KICS Style]

Moon Kyou Song, Min Han Kong, Myoung Seob Lim, "Design of a Variable Shortened and Punctured RS Decoder," The Journal of Korean Institute of Communications and Information Sciences, vol. 31, no. 8, pp. 763-770, 8. 2006.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880