An FPGA Implementation of High-Speed Adaptive Turbo Decoder 


Vol. 32,  No. 4, pp. 379-388, Apr.  2007


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  Abstract

In this paper, we propose an adaptive turbo decoding algorithm for high order modulation scheme combined with originally design for a standard rate-1/2 turbo decoder for B/QPSK modulation. A transformation applied to the incoming I-channel and Q-channel symbols allows the use of an off-the-shelf B/QPSK turbo decoder without any modifications. Adaptive turbo decoder process the received symbols recursively to improve the performance. As the number of iterations increase, the execution time and power consumption also increase as well. The source of the latency and power consumption reduction is from the combination of the radix-4, dual-path processing, parallel decoding, and early-stop algorithms. We implemented the proposed scheme on a field-programmable gate array (FPGA) and compared its decoding speed with that of a conventionaldecoder.From the result of implementation, we confirm that the decoding speed of proposed adaptive decoding is faster than conventional scheme by 6.4 times.

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  Cite this article

[IEEE Style]

M. H. Kim, J. Jung, J. T. Bae, S. S. Choi, I. K. Lee, "An FPGA Implementation of High-Speed Adaptive Turbo Decoder," The Journal of Korean Institute of Communications and Information Sciences, vol. 32, no. 4, pp. 379-388, 2007. DOI: .

[ACM Style]

Min Huyk Kim, Ji-Won Jung, Jong Tae Bae, Seok Soon Choi, and In Ki Lee. 2007. An FPGA Implementation of High-Speed Adaptive Turbo Decoder. The Journal of Korean Institute of Communications and Information Sciences, 32, 4, (2007), 379-388. DOI: .

[KICS Style]

Min Huyk Kim, Ji-Won Jung, Jong Tae Bae, Seok Soon Choi, In Ki Lee, "An FPGA Implementation of High-Speed Adaptive Turbo Decoder," The Journal of Korean Institute of Communications and Information Sciences, vol. 32, no. 4, pp. 379-388, 4. 2007.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880