Design of Digital Signal Processor for Ethernet Receiver Using TP Cable 


Vol. 32,  No. 8, pp. 785-793, Aug.  2007


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  Abstract

This paper presents the digital signal processing submodule of a 100Base-TX Ethernet receiver to support 100Mbps at TP cable channel. The proposed submodule consists of programmable gain controller, timing recovery, adaptive equalizer and baseline wander compensator. The measured Bit Error Rate is less than 10?¹²BER when continuously receiving data up to 150m. The proposed signal processing submodule is implemented in digital circuits except for PLL and amplifier. The performance improvement of the proposed equalizer and BLW compensator is measured about 1㏈ compared with the existing architecture that removes BLW using errors of an adaptive equalizer. The architecture has been modeled using Verilog-HDL and synthesized using samsung 0.18 ㎛ cell library. The implemented digital signal processing submodule operates at 142.7 ㎒ and the total number of gates are about 128,528.

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  Cite this article

[IEEE Style]

J. Hong and M. Sunwoo, "Design of Digital Signal Processor for Ethernet Receiver Using TP Cable," The Journal of Korean Institute of Communications and Information Sciences, vol. 32, no. 8, pp. 785-793, 2007. DOI: .

[ACM Style]

Ju-hyung Hong and Myung-hoon Sunwoo. 2007. Design of Digital Signal Processor for Ethernet Receiver Using TP Cable. The Journal of Korean Institute of Communications and Information Sciences, 32, 8, (2007), 785-793. DOI: .

[KICS Style]

Ju-hyung Hong and Myung-hoon Sunwoo, "Design of Digital Signal Processor for Ethernet Receiver Using TP Cable," The Journal of Korean Institute of Communications and Information Sciences, vol. 32, no. 8, pp. 785-793, 8. 2007.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880