Modeling of Pipeline A/D converter with Verilog-A 


Vol. 32,  No. 10, pp. 1019-1024, Oct.  2007


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  Abstract

In this paper, the 10bit 20㎒ pipelined analog-to-digital converter that is able to apply to WLAN system was modeled for ADC design. Each blocks in converter such as sample and hold amplifier(SHA), comparator, multiplyng DAC(MDAC), and digital correction logic(DCL) was modeled. The pipelined ADC with these modeled blocks takes 1/50 less time than the one of simulation using HSPICE.

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  Cite this article

[IEEE Style]

S. Park, J. Lee, K. Yoon, "Modeling of Pipeline A/D converter with Verilog-A," The Journal of Korean Institute of Communications and Information Sciences, vol. 32, no. 10, pp. 1019-1024, 2007. DOI: .

[ACM Style]

Sang-wook Park, Jae-yong Lee, and Kwang-Sub Yoon. 2007. Modeling of Pipeline A/D converter with Verilog-A. The Journal of Korean Institute of Communications and Information Sciences, 32, 10, (2007), 1019-1024. DOI: .

[KICS Style]

Sang-wook Park, Jae-yong Lee, Kwang-Sub Yoon, "Modeling of Pipeline A/D converter with Verilog-A," The Journal of Korean Institute of Communications and Information Sciences, vol. 32, no. 10, pp. 1019-1024, 10. 2007.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880