Design of an Automatic Generation System for Embedded Processor Cores with Minimal Power Consumption 


Vol. 32,  No. 10, pp. 1042-1050, Oct.  2007


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  Abstract

This paper describes the system which automatically generates power-minimized embedded cores from MDL descriptions. An automatic generation system is constructed which generated embedded cores which consumes less power for application programs. From the usage information on pipeline stages for each instruction, the proposed system generates embedded cores with the capability of detecting/resolving pipeline hazards. The generated cores are configured such that the power consumption is minimized. The proposed system has been tested by generating HDL codes for ARM9, MIPS R3000 architectures. Experimental results show functional accuracy of the generated cores, and show that power reduction of 20%～40% has been observed for benchmark programs.

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  Cite this article

[IEEE Style]

D. Kim and S. Hwang, "Design of an Automatic Generation System for Embedded Processor Cores with Minimal Power Consumption," The Journal of Korean Institute of Communications and Information Sciences, vol. 32, no. 10, pp. 1042-1050, 2007. DOI: .

[ACM Style]

Dong-Won Kim and Sun-Young Hwang. 2007. Design of an Automatic Generation System for Embedded Processor Cores with Minimal Power Consumption. The Journal of Korean Institute of Communications and Information Sciences, 32, 10, (2007), 1042-1050. DOI: .

[KICS Style]

Dong-Won Kim and Sun-Young Hwang, "Design of an Automatic Generation System for Embedded Processor Cores with Minimal Power Consumption," The Journal of Korean Institute of Communications and Information Sciences, vol. 32, no. 10, pp. 1042-1050, 10. 2007.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880