Adaptive Bit-Reliability Mapping for LDPC-Coded High-Order Modulation Systems 


Vol. 32,  No. 12, pp. 1135-1141, Dec.  2007


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  Abstract

In this paper, an adaptive bit-reliability mapping is proposed for the bit-level Chase combining in LDPC-coded high-order modulation systems. Contrary to the previously known bit-reliability mapping that assigns the information (or parity) bits to more (or less) reliable bit positions, the proposed mapping adaptively assigns codeword bits to the bit positions of various reliabilities by considering the characteristics of code and protection levels of bits in high-order modulation symbol. Compared with the symbol-level Chase combining and the constellation rearrangement bit mapping, the proposed mapping gives 0.7~1.3 ㏈ and 0.1~1.0 ㏈ performance gain at FER=10?³ with no additional complexity, respectively. Adaptive bit-reliability mappings are derived for various environments and the validity of them is confirmed through simulation.

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  Cite this article

[IEEE Style]

H. Joo, D. Shin, S. Hong, "Adaptive Bit-Reliability Mapping for LDPC-Coded High-Order Modulation Systems," The Journal of Korean Institute of Communications and Information Sciences, vol. 32, no. 12, pp. 1135-1141, 2007. DOI: .

[ACM Style]

Hyeong-Gun Joo, Dong-Joon Shin, and Song-Nam Hong. 2007. Adaptive Bit-Reliability Mapping for LDPC-Coded High-Order Modulation Systems. The Journal of Korean Institute of Communications and Information Sciences, 32, 12, (2007), 1135-1141. DOI: .

[KICS Style]

Hyeong-Gun Joo, Dong-Joon Shin, Song-Nam Hong, "Adaptive Bit-Reliability Mapping for LDPC-Coded High-Order Modulation Systems," The Journal of Korean Institute of Communications and Information Sciences, vol. 32, no. 12, pp. 1135-1141, 12. 2007.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880