An Area Efficient Network Interface Architecture 


Vol. 33,  No. 5, pp. 361-370, May  2008


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  Abstract

NoC is adopted for data communication between processors and IPs in MPSoC system. NoC has an advantage of scalability in that system can be easily expanded just by adding switches. However, as the number of switches increases, chip area increases as well as data transfer latency. This paper proposes an architecture that can reduce the number of switches in the system by sharing network interfaces. To reduce NI area, the modules sharing network interface use a common buffer in network interface. Experimental results show that the chip area has been reduced by 46.5% and data transfer latency by 17.1%, respectively, compared to conventional architecture.

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  Cite this article

[IEEE Style]

S. Lee and S. Hwang, "An Area Efficient Network Interface Architecture," The Journal of Korean Institute of Communications and Information Sciences, vol. 33, no. 5, pp. 361-370, 2008. DOI: .

[ACM Style]

Ser-Hoon Lee and Sun-Young Hwang. 2008. An Area Efficient Network Interface Architecture. The Journal of Korean Institute of Communications and Information Sciences, 33, 5, (2008), 361-370. DOI: .

[KICS Style]

Ser-Hoon Lee and Sun-Young Hwang, "An Area Efficient Network Interface Architecture," The Journal of Korean Institute of Communications and Information Sciences, vol. 33, no. 5, pp. 361-370, 5. 2008.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880